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8 bit microcontroller 870c series TMP86FS49FG
page 2 TMP86FS49FG the information contained herein is subject to change without notice. the information contained he rein is presented only as a guide for the applications of our products. no responsibility is assumed by tosh iba for any infringements of patents or other rights of the third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of toshiba or others. toshiba is continually working to improve the qual ity and reliability of its products. nevertheless, semiconductor devices in general can malfunction or fa il due to their inherent electrical sensitivity and vulnerability to physical stress. it is the responsibility of the buyer, when utilizing toshiba products , to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that to shiba products are used within specified operating ranges as set forth in the most re cent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?handling guide for semiconductor devices,? or ?toshiba semiconductor reliability handbook? etc.. the toshiba products listed in this document are inte nded for usage in general electronics applications ( computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury (?unintended usage?). unintended usage include atomic energy control instruments, airplane or spaceship instruments, tr ansportation instruments, traffic signal instruments, combustion control instruments, medical instrument s, all types of safety devices, etc.. unintended usage of toshiba products listed in this docume nt shall be made at the customer?s own risk. the products described in this document may include products subject to the foreign exchange and foreign trade laws. toshiba products should not be embedded to the downstream products which are prohibited to be produced and sold, under any law and regulations. for a discussion of how the reliability of microcontro llers can be predicted, please refer to section 1.3 of the chapter entitled quality and re liability assurance/handling precautions. ? 2004 toshiba corporation all rights reserved
page 1 this product uses the super fl a sh ? technology under the licence of sillicon storage technology,inc. super flash ? is registered trademark of sillicon storage technology,inc. purchase of toshiba i 2 c components conveys a license under the philips i 2 c patent rights to use these components in an i 2 c system, provided that the system conforms to the i 2 c standard specificati on as defined by philips. 030619ebp1 TMP86FS49FG cmos 8-bit microcontroller ? the information contained herein is subject to change without notice. ? the information contained herein is present ed only as a guide for the applications of our products. no responsibility is assum ed by toshiba for any infringements of patents or other rights of the th ird parties which may result from its use. no license is gran ted by impli- cation or otherwise under any patent or patent rights of toshiba or others. ? toshiba is continually working to improve the quality and reli ability of its products. neverthel ess, semiconductor devices in general can malfunction or fail due to their inherent el ectrical sensitivity and vul nerability to physical stre ss. it is the responsibility of the buyer, when utilizing toshiba products, to comply with the standards of sa fety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such toshiba products could cause loss of human life, bodily injury or damage to property. in developing your designs, please ensure that toshiba products are used within s pecified operating ranges as set forth in the most recent toshiba products specifications. also, please keep in mind the precautions and conditions set forth in the ?g handling guide for semiconductor devices, ?h or ?g toshiba semiconductor reliability handbook ?h etc.. ? the toshiba products listed in this document are intended for usage in general electronics applic ations (computer, personal eq uip- ment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). these toshiba products are neithe r intended nor warranted for usage in equipment that requires extr aordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ( ?g unintended usage ?h ). unintended usage include atomic energy control instru- ments, airplane or spaceship instruments, transportation instrument s, traffic signal instruments, combustion control instrumen ts, medical instruments, all types of safety devices, etc.. unintended usage of toshiba products listed in this document shall be made at t he customer ?f s own risk. ? the products described in this document are subjec t to the foreign exchange and foreign trade laws. ? toshiba products should not be embedded to the downstream produc ts which are prohibited to be produced and sold, under any law and regulations. ? for a discussion of how the reliability of microcontrollers c an be predicted, please refer to section 1.3 of the chapter entit led quality and reliability assurance/ handling precautions. TMP86FS49FG 1.1 features 1. 8-bit single chip microcomputer tlcs-870/c series - instruction execution time : 0.25 s (at 16 mhz) 122 s (at 32.768 khz) - 132 types & 731 basic instructions 2. 24interrupt sources (external : 5 internal : 19) 3. input / output ports (56pins) 4. time base timer 5. watchdog timer 6. 16-bit timer counter: 1 ch - timer, external trigger, window , pulse width measurement, event counter, ppg(programmable pulse generator) output modes 7. 16-bit timer counter : 1ch - timer, event counter, window modes 8. 8-bit timer counter : 4ch timer, event counter, pwm(pulse width modulation) output, pdo(programmable divider output) out- put and ppg(programmable pulse generator) modes 9. 8-bit uart: 2ch 10. high-speed sio: 2ch 11. serial bus interface(i 2 c bus): 1ch product no. flash ram package mask mcu TMP86FS49FG 60k bytes 2k bytes p-qfp64-1414-0.80a tmp86ch49/cm49 tentative
page 2 1.1 features TMP86FS49FG 12. 10-bit successive approximation type ad converter analog inputs: 16ch 13. key on wake up : 4ch 14. clock operation single clock mode dual clock mode 15. low power consumption operation stop mode: oscillation stops. (battery/capacitor back-up.) slow1 mode: low power consumption operation usin g low-frequency clock.(high-frequency clock stop.) slow2 mode: low power consumption operation usin g low-frequency clock.(high-frequency clock oscillate.) idle0 mode: cpu stops, and only the time-based-tim er(tbt) on peripherals operate using high fre- quency clock. release by falling edge of th e source clock which is set by tbtcr. idle1 mode: cpu stops and peripherals operate us ing high frequency clock. release by interru- puts(cpu restarts). idle2 mode: cpu stops and peripherals operate usin g high and low frequency clock. release by inter- ruputs. (cpu restarts). sleep0 mode: cpu stops, and only the time-based-t imer(tbt) on peripherals operate using low fre- quency clock.release by falling edge of th e source clock which is set by tbtcr. sleep1 mode: cpu stops, and peripherals operate using low frequency clock. release by interru- put.(cpu restarts). sleep2 mode: cpu stops and peripherals operate using high and low frequency clock. release by interruput. 16. wide operation voltage: 4.5 v~ 5.5 v at 16.0 mhz /32.768 khz 3.0 v~ 3.6 v at 8 mhz /32.768 khz tentative
page 3 TMP86FS49FG 1.2 pin assignment figure 1-1 pin assignment vss xout test vdd (xtin) p21 (xtout) p22 reset ( stop / int5 ) p20 ( int0 ) p00 (txd1) p02 (si1) p04 (int1) p03 (so1) p05 ( sck1 ) p06 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 p65(ain05/stop1) p67(ain07/stop3) p70(ain10) p72(ain12) p71(ain11) p74(ain14) p73(ain13) p66(ain06/stop2) p14 (tc4/ pdo4/pwm4/ppg4 ) p13 (tc3/ pdo3/pwm3 ) p12 ( ppg ) p11 ( dvo ) p10 (tc1) p47 p46 ( sck2 ) p45 (so2) (boot/rxd1) p01 xin p07(int2) avdd p60(ain00) p61(ain01) p64(ain04/stop0) p62(ain02) varef p63(ain03) p44 (si2) p43 p42 (txd2) p41 (rxd2) p40 p77 (ain17) p76 (ain16) p75 (ain15) (int3/tc2) p15 ( pdo5/pwm5 /tc5) p16 ( pdo6/pwm6/ppg6 /tc6) p17 (scl) p50 (sda) p51 p52 p53 p54 p30 p31 p32 p33 p34 p35 p36 p37 tentative
page 4 1.3 block diagram TMP86FS49FG 1.3 block diagram figure 1-2 block diagram tentative
page 5 TMP86FS49FG 1.4 pin names and functions table 1-1 pin names and functions ?i 1/3 ?j pin name pin number input/output functions p07 int2 17 io i port07 external interrupt 2 input p06 sck1 16 io io port06 serial clock input/output 1 p05 so1 15 io o port05 serial data output 1 p04 si1 14 io i port04 serial data input 1 p03 int1 13 io i port03 external interrupt 1 input p02 txd1 12 io o port02 uart data output 1 p01 rxd1 boot 11 io i i port01 uart data input 1 serial prom mode control input p00 int0 10 io i port00 external interrupt 0 input p17 tc6 pdo6/pwm6/ppg6 51 io i o port17 timer counter 6 input pdo6/pwm6/ppg6 output p16 tc5 pdo5/pwm5 50 io i o port16 timer counter 5 input pdo5/pwm5 output p15 tc2 int3 49 io i i port15 timer counter 2 input external interrupt 3 input p14 tc4 pdo4/pwm4/ppg4 48 io i o port14 timer counter 4 input pdo4/pwm4/ppg4 output p13 tc3 pdo3/pwm3 47 io i o port13 timer counter 3 input pdo3/pwm3 output p12 ppg 46 io i port12 ppg output p11 dvo 45 io o port11 divider output p10 tc1 44 io i port10 timer counter 1 input p22 xtout 7 io o port22 resonator connecting pins(32.768 khz) for inputting external clock p21 xtin 6 io i port21 resonator connecting pins(32.768 khz) for inputting external clock p20 int5 stop 9 io i i port20 external interrupt 5 input stop mode release signal input tentative
page 6 1.4 pin names and functions TMP86FS49FG p37 64 io port37 p36 63 io port36 p35 62 io port35 p34 61 io port34 p33 60 io port33 p32 59 io port32 p31 58 io port31 p30 57 io port30 p47 43 io port47 p46 sck2 42 io io port46 serial clock input/output 2 p45 so2 41 io o port45 serial data output 2 p44 si2 40 io i port44 serial data input 2 p43 39 io port43 p42 txd2 38 io o port42 uart data output 2 p41 rxd2 37 io i port41 uart data input 2 p40 36 io port40 p54 56 io port54 p53 55 io port53 p52 54 io port52 p51 sda 53 io io port51 i2c bus serial data input/output p50 scl 52 io io port50 i2c bus serial clock input/output p67 ain07 stop3 27 io i i port67 ad converter analog input 7 stop3 input p66 ain06 stop2 26 io i i port66 ad converter analog input 6 stop2 input p65 ain05 stop1 25 io i i port65 ad converter analog input 5 stop1 input p64 ain04 stop0 24 io i i port64 ad converter analog input 4 stop0 input p63 ain03 23 io i port63 ad converter analog input 3 p62 ain02 22 io i port62 ad converter analog input 2 table 1-1 pin names and functions ?i 2/3 ?j pin name pin number input/output functions tentative
page 7 TMP86FS49FG p61 ain01 21 io i port61 ad converter analog input 1 p60 ain00 20 io i port60 ad converter analog input 0 p77 ain17 35 io i port77 ad converter analog input 17 p76 ain16 34 io i port76 ad converter analog input 16 p75 ain15 33 io i port75 ad converter analog input 15 p74 ain14 32 io i port74 ad converter analog input 14 p73 ain13 31 io i port73 ad converter analog input 13 p72 ain12 30 io i port72 ad converter analog input 12 p71 ain11 29 io i port71 ad converter analog input 11 p70 ain10 28 io i port70 ad converter analog input 10 xin 2 i resonator connecting pins for high-frequency clock xout 3 o resonator connecting pins for high-frequency clock reset 8 i reset signal input test 4 i test pin for out-going test and the serial prom mode control pin. usually fix to low level. fix to high level when the serial prom mode starts. varef 18 i analog reference voltage input (high) avdd 19 i ad circuit power supply vdd 5 i +5v vss 1 i 0(gnd) table 1-1 pin names and functions ?i 3/3 ?j pin name pin number input/output functions tentative
page 8 1.4 pin names and functions TMP86FS49FG tentative
page 9 TMP86FS49FG 2. operational description 2.1 cpu core functions the cpu core consists of a cpu, a system cl ock controller, and an interrupt controller. this section provides a description of the cpu core, the program memory, the data memory, and the reset circuit. 2.1.1 memory address map the TMP86FS49FG memory consists of 4 blocks: flash, ram, dbr (data buffer register) and sfr (special function register). they are all mapped in 64-kbyte addr ess space. figure 2-1 shows the TMP86FS49FG memory address map. the general-purpose registers are not assigned to the ram address space. figure 2-1 memory address map 64 byte sfr ram dbr 0040 h 2kbyte 083f h 0f80 h 0fff h 1000 h ffff h flash 60kbyte flash : includes; program memory vector table ram: random access memory includes: data memory stack sfr: special function register includes: i/o ports peripheral control registers peripheral status registers system control registers program status word dbr: databuffer register includes: peripheral status registers 003f h 0000 h ffa0 h 128byte tentative
page 10 2. operational description 2.2 system clock controller TMP86FS49FG 2.1.2 program memory (flash) the TMP86FS49FG has a 60k 8 bits (address 1000h to ffffh) of program memory (flash ). a pro- gram code placed on the internal ram can be excuta ble when a certain procedur e is executed ( see "2.3.2 address trap reset "). 2.1.3 data memory (ram) data memory consists of internal data memory (internal flash or ram). the TMP86FS49FG has 2kbyte (address 0040h to 083fh) of internal ram. the first 192 bytes (0040h to 00ffh) of the internal ram are located in the direct area; instru ctions with shorten operations ar e available against such an area. the data memory contents become un stable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. 2.2 system clock controller the system clock controller consists of a clock generator, a timing generator, and a standby controller. figure 2-2 syst em colck control example :clears ram to ?00h?. (TMP86FS49FG) ld hl, 0040h ; start address setup ld a, h ; initial value (00h) setup ld bc, 07ffh ; sramclr: ld (hl), a inc hl dec bc jrs f, sramclr tbtcr syscr2 syscr1 xin xout xtin xtout fc 0036 h 0038 h 0039 h fs timing generator control register timing generator standby controller system clocks clock generator control high-frequency clock oscillator low-frequency clock oscillator clock generator system control registers tentative
page 11 TMP86FS49FG 2.2.1 clock generator the clock generator generates the basic clock which pr ovides the system clocks supplied to the cpu core and peripheral hardware. it contains two oscillation ci rcuits: one for the high-frequency clock and one for the low-frequency clock. power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. the high-frequency (fc) clocks and lo w-frequency (fs) clock can easily be obtained by connecting a resona- tor between the xin/xout and xtin/x tout pins respectively. clock input from an external oscillator is also possible. in this case, extern al clock is applied to xin/xtin pi n with xout/xtout pin not connected. figure 2-3 examples of resonator connection note:the function to monitor the basic clock directly at external is not provided for hardware, however, with dis- abling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. the system to require the adjustment of the oscilla tion frequency should create the program for the adjust- ment in advance. 2.2.2 timing generator the timing generator generates the various system cloc ks supplied to the cpu core and peripheral hardware from the basic clock (fc or fs). the timing generator provides the following functions. 1. generation of main system clock 2. generation of divider output ( dvo ) pulses 3. generation of source clocks for time base timer 4. generation of source clocks for watchdog timer 5. generation of internal source clocks for timer/counters 6. generation of warm-up clocks for releasing stop mode 2.2.2.1 configuration of timing generator the timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. an input clock to the 7th stage of the divider depends on the operating mode, dv7ck (bit4 in tbtcr), that is shown in figure 1-5. as reset an d stop mode started/canceled, the prescaler and the divider are cleared to ?0?. xout xin (open) xout xin xtout xtin (open) xtout xtin (a) crystal/ceramic resonator (b) external oscillator (c) crystal (d) external oscillator high-frequency clock low-frequency clock tentative
page 12 2. operational description 2.2 system clock controller TMP86FS49FG figure 2-4 configurat ion of timing generator note 1: in single clock mode, do not set dv7ck to ?1?. note 2: do not set ?1? on dv7ck while the low-frequency clock is not operated stably. note 3: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *: don?t care note 4: in slow1/2 and sleep1/2 modes, the dv7ck setting is ineffective, and fs is input to the 7th stage of the divider. note 5: when stop mode is entered from normal1/2 mode, the dv 7ck setting is ineffective during the warm-up period after release of stop mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 machine cycle instruction execution and peripheral hardware operat ion are synchronized with the main system clock. the minimum instruction execution uni t is called an ?machine cycle?. th ere are a total of 10 different types of instructions for the tlcs-870/c series: ra nging from 1-cycle instructions which require one machine cycle for execution to 10-cyc le instructions which require 10 machine cycles fo r execution. a machine cycle consists of 4 states (s0 to s3), and each state consists of one main system clock. timing generator control register tbtcr (0036h) 76543210 (dvoen) (dvock) dv7ck (tbten) (tbtck) (initial value: 0000 0000) dv7ck selection of input to the 7th stage of the divider 0: fc/2 8 [hz] 1: fs r/w multi- plexer high-frequency clock fc low-frequency clock fs divider sysck fc/4 fc or fs machine cycle counters main system clock generator 1 2 1 4 3 2 8 7 10 9 12 11 14 13 16 15 dv7ck multiplexer timer/ counters warm-up controller watchdog timer time base timer divider output circuit serial interface a s b y s b0 a0 y0 b1 a1 y1 5 6 17 18 19 20 21 tentative
page 13 TMP86FS49FG figure 2-5 machine cycle 2.2.3 operation mode control circuit the operation mode control circuit starts and stops th e oscillation circuits for the high-frequency and low- frequency clocks, and switches the main system clock. there are two operating modes: single clock and dual clock. these modes are controlled by the system control registers (syscr1 and syscr2). figure 2-6 shows the operating mode transition diagram. 2.2.3.1 single-clock mode only the oscillation circuit for the high-frequenc y clock is used, and p21 (xtin) and p22 (xtout) pins are used as input/output ports . the main-system clock is obtained from the high-frequency clock. in the single-clock mode, the machine cycle time is 4/fc [s]. (1) normal1 mode in this mode, both the cpu core and on-chip pe ripherals operate using the high-frequency clock. the TMP86FS49FG is placed in this mode after reset. (2) idle1 mode in this mode, the internal oscillation circuit remains active. the cpu and the watchdog timer are halted; however on-chip peripherals remain active (operate using the high-frequency clock). idle1 mode is started by syscr2, and id le1 mode is released to normal1 mode by an interrupt request from the on-c hip peripherals or external inte rrupt inputs. when the imf (inter- rupt master enable flag) is ?1? (interrupt enable), th e execution will resume with the acceptance of the interrupt, and the operation will return to normal after the interrupt service is completed. when the imf is ?0? (interrupt disable), the execution will resume with the instruction which follows the idle1 mode start instruction. (3) idle0 mode in this mode, all the circuit, except oscillator an d the timer-base-timer, stops operation. this mode is enabled by setting ?1? on bit tghalt on the system control register 2 (syscr2). when idle0 mode starts, the cpu stops and the timing generator stops feeding the clock to the peripheral circuits other than tbt. then, upon de tecting the falling edge of the source clock selected with tbtcr, the timing generator starts feeding the clock to al l peripheral circuits. 1/fc or 1/fs [s] main system clock (fm) state machine cycle s3 s2 s1 s0 s3 s2 s1 s0 tentative
page 14 2. operational description 2.2 system clock controller TMP86FS49FG when returned from idle0 mode, the cpu rest arts operating, entering normal1 mode back again. idle0 mode is entered and returned regardless of how tbtcr is set. when imf = ?1?, ef6 (tbt interrupt individu al enable flag) = ?1?, and tb tcr = ?1?, interrupt pro- cessing is performed. when idle0 mode is entered while tbtcr = ?1?, the inttbt interrupt latch is set after returning to normal1 mode. 2.2.3.2 dual-clock mode both the high-frequency and low-frequency oscillatio n circuits are used in th is mode. p21 (xtin) and p22 (xtout) pins cannot be used as input/output ports. the main system clock is obtained from the high-frequency clock in normal2 and idle2 modes, and is obtained from the low-frequency clock in slow and sleep modes. th e machine cycle time is 4/fc [s] in the normal2 and idle2 modes, and 4/fs [s] (122 ms at fs = 32.768 khz) in the slow and sleep modes. the tlcs-870/c is placed in the signal-clock mode during reset. to use the dual-clock mode, the low- frequency oscillator should be turned on at the start of a program. (1) normal2 mode in this mode, the cpu core operates with the high-frequency clock. on-chip peripherals operate using the high-frequency clock and/or low-frequency clock. (2) slow2 mode in this mode, the cpu core operates with the lo w-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. on-chip peripheral s are triggered by the low-fre- quency clock. as the sysck on syscr2 becomes ?0?, the hardware changes into normal2 mode. as the xen on syscr2 becomes ?0?, the ha rdware changes into slow1 mode. do not clear xten to ?0? during slow2 mode. (3) slow1 mode this mode can be used to reduce power-consu mption by turning off oscillation of the high-fre- quency clock. the cpu core and on-chip peri pherals operate using th e low-frequency clock. switching back and forth between slow1 and slow2 modes are performed by xen bit on the system control register 2 (syscr2). in slow1 an d sleep modes, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. (4) idle2 mode in this mode, the internal oscillation circuit remain active. the cpu and the watchdog timer are halted; however, on-chip peripherals remain activ e (operate using the high-frequency clock and/or the low-frequency clock). starting and releasing of idle2 mode are the same as for idle1 mode, except that operation re turns to normal2 mode. (5) sleep1 mode in this mode, the internal oscillation circuit of the low-frequency clock remains active. the cpu, the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; how- ever, on-chip peripherals remain active (operate us ing the low-frequency clock). starting and releas- ing of sleep mode are the same as for idle1 mode, except that op eration returns to slow mode. in slow and sleep modes, the input clock to th e 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. tentative
page 15 TMP86FS49FG (6) sleep2 mode the sleep2 mode is the idle mode corresponding to the slow2 mode. the status under the sleep2 mode is same as that under the sleep1 mo de, except for the oscilla tion circuit of the high- frequency clock. (7) sleep0 mode in this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. this mode is enabled by setting ?1? on bit tghalt on the system control register 2 (syscr2). when sleep0 mode starts, the cp u stops and the timing generator stops feeding the clock to the peripheral circuits other than tbt. then, upon de tecting the falling edge of the source clock selected with tbtcr, the timing generator starts feeding the clock to al l peripheral circuits. when returned from sleep0 mode, the cpu restarts operating, entering slow1 mode back again. sleep0 mode is entered and returned re gardless of how tbtcr is set. when imf = ?1?, ef6 (tbt interrupt individual enable flag ) = ?1?, and tbtcr = ?1?, interrupt pro- cessing is performed. when sleep0 mode is entered while tbtcr = ?1?, the inttbt interrupt latch is set after returning to slow1 mode. 2.2.3.3 stop mode in this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. the internal status immediately prior to the halt is held with a lowest power consumption during stop mode. stop mode is started by the syst em control register 1 (syscr1), an d stop mode is released by a inputting (either level-sensitive or edge-sens itive can be programmably selected) to the stop pin. after the warm-up period is completed, the execution resumes with the instruction which follows the stop mode start instruction. note 1: normal1 and normal2 modes are generically called no rmal; slow1 and slow2 are called slow; idle0, idle1 and idle2 are called idle; sleep0, sleep1 and sleep2 are called sleep. note 2 syscr2 = "1" stop pin input stop pin input stop pin input interrupt interrupt syscr2 = "0" syscr2 = "1" syscr2 = "0" syscr2 = "0" syscr1 = "1" syscr1 = "1" syscr1 = "1" syscr2 = "1" syscr2 = "1" interrupt syscr2 = "1" syscr2 = "1" interrupt syscr2 = "1" reset release normal1 mode idle0 mode (a) single-clock mode idle1 mode normal2 mode idle2 mode syscr2 = "1" slow2 mode sleep2 mode slow1 mode sleep1 mode sleep0 mode reset (b) dual-clock mode stop syscr2 = "1" note 2 tentative
page 16 2. operational description 2.2 system clock controller TMP86FS49FG note 2: the mode is released by fa lling edge of tbtcr setting. figure 2-6 operating mode transition diagram note 1: always set retm to ?0? when transiting from normal mode to stop mode. always set retm to ?1? when transiting from slow mode to stop mode. note 2: when stop mode is released with reset pin input, a return is made to normal1 regardless of the retm contents. note 3: fc: high-frequency clock [hz], fs : low-frequency clock [hz], *; don?t care note 4: bits 1 and 0 in syscr1 are read as undefined data when a read instruction is executed. note 5: as the hardware becomes stop mode under outen = ?0?, input value is fixed to ?0?; therefore it may cause interrupt request on account of falling edge. note 6: when the key-on wakeup is used, the edge realease can not function according to some conditions. it is recommended to set the level realease (relm = ?1?). note 7: port p20 is used as stop pin. therefore, when stop mode is started, outen does not affect to p20, and p20 becomes high-z mode. note 8: the warmig-up time should be set correctly for using oscillator. operating mode oscillator cpu core tbt other peripherals machine cycle time high frequency low frequency single clock reset oscillation stop reset reset reset 4/fc [s] normal1 operate operate operate idle1 halt idle0 halt ? stop stop halt dual clock normal2 oscillation oscillation operate with high frequency operate operate 4/fc [s] idle2 halt slow2 operate with low frequency 4/fs [s] sleep2 halt slow1 stop operate with low frequency sleep1 halt sleep0 halt ? stop stop halt system control register 1 syscr1 (0038h) 76543210 stop relm retm outen wut (initial value: 0000 00**) stop stop mode start 0: cpu core and peripherals remain active 1: cpu core and peripherals are halted (start stop mode) r/w relm release method for stop mode 0: edge-sensitive release 1: level-sensitive release retm operating mode after stop mode 0: return to normal1/2 mode 1: return to slow1 mode outen port output during stop mode 0: high impedance 1: output kept wut warm-up time at releasing stop mode return to normal mode return to slow mode 00 3 2 16 /fc 3 2 13 /fs 01 2 16 /fc 2 13 /fs 10 3 2 14 /fc 3 2 6 /fs 11 2 14 /fc 2 6 /fs tentative
page 17 TMP86FS49FG note 1: a reset is applied if both xen and xten are cleared to ?0?, xen is cleared to ?0? when sysck = ?0?, or xten is cleared to ?0? when sysck = ?1?. note 2: *: don?t care, tg: timing generator note 3: bits 3, 1 and 0 in syscr2 are always read as undefined value. note 4: do not set idle and tghalt to ?1? simultaneously. note 5: because returning from idle0/sleep0 to normal1/slow 1 is executed by the asynchronous internal clock, the period of idle0/sleep0 mode might be shorter than the period setting by tbtcr. note 6: when idle1/2 or sleep1/2 mode is rel eased, idle is automatically cleared to ?0?. note 7: when idle0 or sleep0 mode is released, tghalt is automatically cleared to ?0?. note 8: before setting tghalt to ?1?, be sure to stop peripheral s. if peripherals are not stopped, the interrupt latch of periph erals may be set after idle0 or sleep0 mode is released. 2.2.4 operating mode control 2.2.4.1 stop mode stop mode is controlled by the system control register 1, the stop pin input . the stop pin is also used both as a port p20 and an int5 (external interrupt input 5) pin. stop mode is started by setting stop (bit7 in sy scr1) to ?1?. during stop mode, the following status is maintained. 1. oscillations are turned off, and all internal operations are halted. 2. the data memory, registers, the program status wo rd and port output latches are all held in the status in effect before stop mode was entered. 3. the prescaler and the divider of th e timing generator are cleared to ?0?. 4. the program counter holds the address 2 ahead of th e instruction (e.g., [set (syscr1).7]) which started stop mode. stop mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be selected with the relm (bit6 in syscr1). note 1: during stop period (from start of stop mode to end of warm up), due to changes in the external interrupt pin signal, interrupt latches may be set to ?1? and interrupts may be accepted immediately after stop mode is released. before starting stop mode, therefore, disable interrupts. also, before enabling interrupts after stop mode is rel eased, clear unnecessary interrupt latches. (1) level-sensitive release mode (relm = ?1?) in this mode, stop mode is released by setting the stop pin high. this mode is used for capacitor backup when the main power supply is cut off and long term battery backup. system control register 2 syscr2 (0039h) 76543210 xen xten sysck idle tghalt (initial value: 1000 *0**) xen high-frequency oscillator control 0: turn off oscillation 1: turn on oscillation r/w xten low-frequency oscillator control 0: turn off oscillation 1: turn on oscillation sysck main system clock select (write)/main system clock moni- tor (read) 0: high-frequency clock 1: low-frequency clock idle cpu and watchdog timer control (idle1/2 and sleep1/2 modes) 0: cpu and watchdog timer remain active 1: cpu and watchdog timer are stopped (start idle1/2 and sleep1/2 modes) tghalt tg control (idle0 and sleep0 modes) 0: feeding clock to all peripherals from tg 1: stop feeding clock to peripherals except tbt from tg. (start idle0 and sleep0 modes) tentative
page 18 2. operational description 2.2 system clock controller TMP86FS49FG when the stop pin input is high, executing an instruction which starts stop mode will not place in stop mode but instead will immediately star t the release sequence (w arm up). thus, to start stop mode in the level-sensitive release mode, it is necessary for the prog ram to first confirm that the stop pin input is low. the following two methods can be used for confirmation. 1. testing a port p20. 2. using an external interrupt input int5 ( int5 is a falling edge-sensitive input). figure 2-7 level-s ensitive release mode note 1: in this case of changing to the level-s ensitive mode from the edge-s ensitive mode, the release mode is not switched until a rising edge of the stop pin input is detected. (2) edge-sensitive release mode (relm = ?0?) in this mode, stop mode is released by a rising edge of the stop pin input. this is used in appli- cations where a relatively short pr ogram is executed repeat edly at periodic intervals. this periodic signal (for example, a clock from a low-power consumption oscillator) is input to the stop pin. in the edge-sensitive release mode, stop mode is started even when the stop pin input is high level. example 1 :starting stop mode from normal mode by testing a port p20. ld (syscr1), 01010000b ; sets up the level-sensitive release mode sstoph: test (p2prd). 0 ; wait until the stop pin input goes low level jrs f, sstoph di ; imf 0 set (syscr1). 7 ; starts stop mode example 2 :starting stop mode from normal mode with an int5 interrupt. pint5: test (p2prd). 0 ; to reject noise, stop mode does not start if jrs f, sint5 port p20 is at high ld (syscr1), 01010000b ; sets up the level-sensitive release mode. di ; imf 0 set (syscr1). 7 ; starts stop mode sint5: reti example :starting stop mode from normal mode di ; imf 0 ld (syscr1), 10010000b ; starts after specified to the edge-sensitive release mode v ih normal operation warm up stop operation confirm by program that the stop pin input is low and start stop mode. always released if the stop pin input is high. stop pin xout pin stop mode is released by the hardware. normal operation tentative
page 19 TMP86FS49FG figure 2-8 edge-sensitive release mode stop mode is released by the following sequence. 1. in the dual-clock mode, when returning to normal2, both the high-frequency and low- frequency clock oscillators are turned on; when returning to slow1 mode, only the low- frequency clock oscillator is turned on. in the single-clock mode, only the high-frequency clock oscillator is turned on. 2. a warm-up period is inserted to allow oscillation time to stabilize. during warm up, all internal operations remain halted. four differ ent warm-up times can be selected with the wut (bits 2 and 3 in syscr1) in accord ance with the resona tor characteristics. 3. when the warm-up time has elapsed, normal operation resumes with the instruction follow- ing the stop mode start instruction. the start is made after the prescaler and the divider of the timing generator are cleared to ?0?. note: the warm-up time is obtained by dividing the basic clock by the divider. therefore, the warm-up time may include a certain amount of error if t here is any fluctuation of the oscillation frequency when stop mode is released. thus, the warm-u p time must be considered as an approximate value. stop mode can also be released by inputting low level on the reset pin, which immediately per- forms the normal reset operation. note: when stop mode is released with a low hold voltage, the following cautions must be observed. the power supply voltage must be at the operating voltage level before releasing stop mode. the reset pin input must also be ?h? level, rising t ogether with the power supply voltage. in this case, if an external time const ant circuit has been connected, the reset pin input voltage will increase at a slower pace than the power supply voltage. at this time, there is a danger that a reset may occur if input voltage level of the reset pin drops below the non-inverting high-level input voltage (hysteresis input). table 2-1 warm-up time example (at fc = 16.0 mhz, fs = 32.768 khz) wut warm-up time [ms] return to normal mode return to slow mode 00 12.288 750 01 4.096 250 10 3.072 5.85 11 1.024 1.95 normal operation normal operation v ih stop mode is released by the hardware at the rising edge of stop pin input. warm up stop mode started by the program. stop operation stop operation stop pin xout pin tentative
page 20 2. operational description 2.2 system clock controller TMP86FS49FG figure 2-9 stop mode start/release instruction address a + 4 0 instruction address a + 3 turn on turn on warm up 0 n halt set (syscr1). 7 turn off (a) stop mode start (example: start with set (syscr1). 7 instruction located at address a) a + 6 a + 5 a + 4 a + 3 a + 2 n + 2 n + 3 n + 4 a + 3 n + 1 instruction address a + 2 2 1 0 3 (b) stop mode release count up turn off halt oscillator circuit program counter instruction execution divider main system clock oscillator circuit stop pin input program counter instruction execution divider main system clock tentative
page 21 TMP86FS49FG 2.2.4.2 idle1/2 mode and sleep1/2 mode idle1/2 and sleep1/2 modes are controlled by the system control register 2 (syscr2) and maskable interrupts. the following status is maintained during these modes. 1. operation of the cpu and watchdog timer (wdt) is halted. on-chip peripherals continue to operate. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. the program counter holds the address 2 ahead of th e instruction which starts these modes. figure 2-10 idle1/ 2 and sleep1/2 modes (1) start the idle1/2 and sleep1/2 modes when idle1/2 and sleep1/2 modes start, set sy scr2 to ?1?. after imf is set to "0", set the individual interrupt enable flag (e f) which releases id le1/2 and sleep1/2. (2) release the idle1/ 2 and sleep1/2 modes idle1/2 and sleep1/2 modes include a normal release mode and an interrupt release mode. these modes are selected by interrupt master en able flag (imf). after releasing idle1/2 and sleep1/2 modes, the syscr2 is automati cally cleared to ?0? and the operation mode is returned to the mode precedin g idle1/2 and sleep1/2 modes. idle1/2 and sleep1/2 modes can also be released by inputting low level on the reset pin. after releasing reset, the operation mode is started from normal1 mode. reset reset input no yes (interrupt release mode) yes no no starting idle1/2 and sleep1/2 modes by instruction cpu and wdt are halted interrupt request imf = 1 interrupt processing execution of the instruction which follows the idle1/2 and sleep1/2 modes start instruction normal release mode yes tentative
page 22 2. operational description 2.2 system clock controller TMP86FS49FG (3) normal release mode (imf = ?0?) idle1/2 and sleep1/2 modes are released by any interrupt source enabled by the individual interrupt enable flag (ef). after the interrupt is ge nerated, the program operation is resumed from the instruction following the idle1/2 and sleep1/2 mo des start instruction. normally, the interrupt latches (il) of the interrupt source used for releas ing must be cleared to ?0? by load instructions. (4) interrupt release mode (imf = ?1?) idle1/2 and sleep1/2 modes are released by any interrupt source enabled with the individual interrupt enable flag (ef) and the interrupt processi ng is started. after the interrupt is processed, the program operation is resumed from the instruction following the instruction, which starts idle1/2 and sleep1/2 modes. note: when a watchdog timer interrupts is generated immediately before idle1/2 and sleep1/2 mode are started, the watchdog timer interrupt will be processed but idle1/2 and sleep1/2 mode will not be started. tentative
page 23 TMP86FS49FG figure 2-11 idle1/2 and sleep1/2 modes start/release (b) idle1/2 and sleep1/2 modes release halt halt halt halt operate instruction address a + 2 a + 3 a + 2 a + 4 a + 3 a + 3 halt set (syscr2). 4 (a) idle1/2 and sleep1/2 modes start (example: starting with the set instruction located at address a) operate operate operate acceptance of interrupt normal release mode interrupt release mode main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer main system clock interrupt request program counter instruction execution watchdog timer tentative
page 24 2. operational description 2.2 system clock controller TMP86FS49FG 2.2.4.3 idle0 and sleep0 modes (idle0, sleep0) idle0 and sleep0 modes are controlled by the system control register 2 (syscr2) and the time base timer control register (tbtcr). the following stat us is maintained during idle0 and sleep0 modes. 1. timing generator stops feeding clock to peripherals except tbt. 2. the data memory, cpu registers, program status word and port output latches are all held in the status in effect before idle0 and sleep0 modes were entered. 3. the program counter holds the address 2 ahead of the instru ction which starts idle0 and sleep0 modes. note: before starting idle0 or sleep0 mode, be sure to stop (disable) peripherals. figure 2-12 idle 0 and sleep0 modes (1) start the idle0 and sleep0 modes stop (disable) peripherals such as a timer counter. yes (normal release mode) yes (interrupt release mode) no yes reset input cpu and wdt are halted starting idle0 and sleep0 modes by instruction reset tbt source clock falling edge tbtcr = "1" interrupt processing execution of the instruction which follows the idle0 and sleep0 modes start instruction imf = "1" yes tbt interrupt enable no no no no stopping peripherals by instruction yes tentative
page 25 TMP86FS49FG when idle0 and sleep0 modes star t, set syscr2 to ?1?. (2) release the idle0 and sleep0 modes idle0 and sleep0 modes includ e a normal release mode and an interrupt release mode. these modes are selected by interrupt master flag (imf), the individual in terrupt enable flag of tbt and tbtcr. after releasing idle0 and sleep0 modes, th e syscr2 is au tomatically cleared to ?0? and the operation mode is returned to the mode preceding idle0 and sleep0 modes. before starting the idle0 or sleep0 mode, when the tbt cr is set to ?1?, inttbt interrupt latch is set to ?1?. idle0 and sleep0 modes can also be released by inputting low level on the reset pin. after releasing reset, the operation mode is started from normal1 mode. note: idle0 and sleep0 modes start/release wit hout reference to tbtcr setting. (3) normal release mode (imf ?e ef7 ?e tbtcr = ?0?) idle0 and sleep0 modes are released by the source clock falling edge, which is setting by the tbtcr without reference to individual in terrupt enable flag (ef). after the falling edge is detected, the program operation is resumed from the instruction following the idle0 and sleep0 modes start instruction. (4) interrupt release mode (imf ?e ef7 ?e tbtcr = ?1?) idle0 and sleep0 modes are released by the source clock falling edge, which is setting by the tbtcr at inttbt interrupt source enabled w ith the individual interrupt enable flag (ef) and inttbt interrupt processing is started. note 1: because returning from idle0, sleep0 to normal1, slow1 is executed by the asynchro- nous internal clock, the period of idle0, sleep0 mode might be the shorter than the period set- ting by tbtcr. note 2: when a watchdog timer interrupt is generat ed immediately before idle0/sleep0 mode is started, the watchdog timer interrupt will be processed but idle0/sleep0 mode will not be started. tentative
page 26 2. operational description 2.2 system clock controller TMP86FS49FG figure 2-13 idle0 and slee p0 modes start/release halt halt operate instruction address a + 2 halt operate set (syscr2). 2 halt operate acceptance of interrupt halt (b) idle0 and sleep0 modes release (a) idle0 and sleep0 modes start (example: starting with the set instruction located at address a) normal release mode interrupt release mode m a i n system clock interrupt request program counter instruction execution watchdog timer main system clock tbt clock tbt clock program counter instruction execution watchdog timer main system clock program counter instruction execution watchdog timer a + 3 a + 2 a + 4 a + 3 a + 3 tentative
page 27 TMP86FS49FG 2.2.4.4 slow mode slow mode is controlled by the sy stem control register 2 (syscr2). the following is the methods to switch the mode with the warm-up counter (tc4, tc3). (1) switching from normal2 mode to slow1 mode first, set sysck (bit5 in syscr2) to switch th e main system clock to the low-frequency clock for slow2 mode. next, clear xen (bit7 in syscr2) to turn off high-frequency oscillation. note: the high-frequency clock can be co ntinued oscillation in order to return to normal2 mode from slow mode quickly. always turn off oscillat ion of high-frequency clock when switching from slow mode to stop mode. when the low-frequency clock oscillation is unstab le, wait until oscillation stabilizes before per- forming the above operations. the timer/counter 6, 5, 4, 3 (tc6, tc5, tc4, tc3) can conveniently be used to confirm that low-frequency clock oscillation has stabilized. (2) switching from slow1 mode to normal2 mode first, set xen (bit7 in syscr2) to turn on the high-frequency oscillation. when time for stabili- zation (warm up) has been taken by the timer/c ounter 4, 3 (tc4, tc3), clear sysck (bit5 in syscr2) to switch the main system clock to the high-frequency clock. example 1 :switching from normal2 mode to slow1 mode. set (syscr2). 5 ; syscr2 1 (switches the main system clock to the low-frequency clock for slow2) clr (syscr2). 7 ; syscr2 0 (turns off high-frequency oscillation) example 2 :switching to the slow1 mode after low-frequency clock has stabilized. set (syscr2). 6 ; syscr2 1 ld (tc3cr), 43h ; sets mode for tc4, tc3 (16-bit tc, fs for source) ld (tc4cr), 05h ldw (ttreg3), 8000h ; sets warm-up time (depend on oscillator accompanied) di ; imf 0 set (eirh). 1 ; enables inttc4 ei ; imf 1 set (tc4cr). 3 ; starts tc4, 3 : pinttc4: clr (tc4cr). 3 ; stops tc4, 3 set (syscr2). 5 ; syscr2 1 (switches the main system cl ock to the low-frequency clock) clr (syscr2). 7 ; syscr2 0 (turns off high-frequency oscillation) reti : vinttc4: dw pinttc4 ; inttc4 vector table tentative
page 28 2. operational description 2.2 system clock controller TMP86FS49FG note: after sysck is cleared to ?0?, executing the in structions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. note: slow mode can also be released by inputting low level on the reset pin, which immediately performs the reset opera- tion. after reset, TMP86FS49FG are placed in normal1 mode. example :switching from the slow1 mode to the norm al2 mode (fc = 16 mhz, warm-up time is 4.0 ms). set (syscr2). 7 ; syscr2 1 (starts high-frequency oscillation) ld (tc3cr), 63h ; sets mode for tc4, tc3 (16-bit tc, fc for source) ld (tc4cr), 05h ld (ttreg4), 0f8h ; sets warm-up time di ; imf 0 set (eirh). 1 ; enables inttc4 ei ; imf 1 set (tc4cr). 3 ; starts tc4, 3 : pinttc4: clr (tc4cr). 3 ; stops tc4, 3 clr (syscr2). 5 ; syscr2 0 (switches the main system cl ock to the high-frequency clock) reti : vinttc4: dw pinttc4 ; inttc4 vector table high-frequency clock low-frequency clock main system clock sysck tentative
page 29 TMP86FS49FG figure 2-14 switching between the normal2 and slow modes set (syscr2). 7 normal2 mode clr (syscr2). 7 set (syscr2). 5 normal2 mode turn off (a) switching to the slow mode slow1 mode slow2 mode clr (syscr2). 5 (b) switching to the normal2 mode high- frequency clock low- frequency clock main system clock instruction execution sysck xen high- frequency clock low- frequency clock main system clock instruction execution sysck xen slow1 mode warm up during slow2 mode tentative
page 30 2. operational description 2.3 reset circuit TMP86FS49FG 2.3 reset circuit the TMP86FS49FG have four ty pes of reset generation procedures: an exte rnal reset input, an address trap reset, a watchdog timer reset and a system clock reset. table 2- 2 shows on-chip hardware initialization by reset action. the malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initial- ized when power is turned on. the reset pin can reset state at the maximum 24/fc [s] (1.5 s at 16.0 mhz) when power is turned on. 2.3.1 external reset input the reset pin contains a schmitt trigger (hysteresis) with an internal pull-up resistor. when the reset pin is held at ?l? level for at least 3 machin e cycles (12/fc [s]) wi th the power supply volt- age within the operating voltage range and oscillation stab le, a reset is applied and the internal state is initial- ized. when the reset pin input goes high, the reset operation is rele ased and the program execution starts at the vector address stored at addresses fffeh to ffffh. figure 2-15 reset circuit table 2-2 initializing internal status by reset action on-chip hardware initial value on-chip hardware initial value program counter (pc) (fffeh) prescaler and divider of timing generator 0 stack pointer (sp) not initialized general-purpose registers (w, a, b, c, d, e, h, l, ix, iy) not initialized jump status flag (jf) not initialized watchdog timer enable zero flag (zf) not initialized output latches of i/o ports refer to i/o port circuitry carry flag (cf) not initialized half carry flag (hf) not initialized sign flag (sf) not initialized overflow flag (vf) not initialized interrupt master enable flag (imf) 0 interrupt individual enable flags (ef) 0 control registers refer to each of control register interrupt latches (il) 0 ram not initialized internal reset reset vdd malfunction reset output circuit watchdog timer reset address trap reset system clock reset tentative
page 31 TMP86FS49FG 2.3.2 address trap reset if the cpu should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip ram (when wdtcr1 is set to ?1?), dbr or the sfr area, address trap reset will be generated. the reset time is a bout 8/fc to 24/fc [s] (0.5 to 1.5 s at 16.0 mhz). note:the operating mode under address tr apped is alternative of reset or interrupt. the address trap area is alter- native. note 1: address ?a? is in the sfr or on-chip ram (wdtcr1 = ?1?) space. note 2: during reset release, reset vector ?r? is read out, and an instruction at address ?r? is fetched and decoded. figure 2-16 addr ess trap reset 2.3.3 watchdog timer reset refer to 2.4 ?watchdog timer?. 2.3.4 system clock reset clearing both xen and xten (bits 7 and 6 in syscr2 ) to ?0?, clearing xen to ?0? when sysck = ?0?, or clearing xten to ?0? when sysc k = ?1? stops system clock, and cau ses the microcomputer to deadlock. this can be prevented by automatically generating a reset signal whenever xen = xten = ?0?, xen = sysck = ?0?, or xten = ?0?/sysck = ?1? is detected to continue the os cillation. the reset time is about 8/ fc to 24/fc [s] (0.5 to 1.5 s at 16.0 mhz). instruction at address r 16/fc [s] 8/fc to 24/fc [s] instruction execution internal reset jp a reset release address trap is occurred 4/fc to 12/fc [s] tentative
page 32 2. operational description 2.3 reset circuit TMP86FS49FG tentative
page 255 TMP86FS49FG 22. electrical characteristics 22.1 absolute maximum ratings the absolute maximum ratings are rated values which must not be exceeded during operat ion, even for an instant. any one of the ratings must not be exceeded. if any absolute maximum rati ng is exceeded, a device may break down or its performance may be degraded, causi ng it to catch fire or explode resul ting in injury to the user. thus, when designing products which include this de vice, ensure that no absolute maximu m rating value will ever be exceeded. (vss = 0 v) parameter symbol pins ratings unit supply voltage v dd -0.3 to 6.5 v input voltage v in -0.3 to v dd + 0.3 output voltage v out1 -0.3 to v dd + 0.3 output current (per 1 pin) i out1 p0, p1, p4, p6, p7 ports -1.8 ma i out2 p0, p1, p4, p6, p7 ports 3.2 i out3 p3, p5 ports 30 output current (total) i out1 p0, p1, p4, p6, p7 ports 60 i out2 p3, p5 ports 80 power dissipation [topr = 85 c] p d 250 mw soldering temperature (time) tsld 260 (10 s) c storage temperature tstg -55 to 125 operating temperature topr -40 to 85 tentative
page 256 22. electrical characteristics 22.1 absolute maximum ratings TMP86FS49FG 22.2 recommended op erating conditions the recommended operating co nditions for a device are operating conditions under which it can be guaranteed that the device will operate as specified. if the device is us ed under operating conditions other than the recommended operating conditions (supply voltage, operating temperature range, specified ac/dc values etc.), malfunction may occur. thus, when designing products which include this device, ensure that the r ecommended operating conditions for the device are always adhered to. 22.2.1 mcu mode (flash programming or erasing) 22.2.2 mcu mode (except flash programming or erasing) note 1: the supply voltage (v dd ) is divided into two different voltage areas. do not change v dd from condition 1 to condi- tion 2 and vice versa while the mcu is operationg. if you wish to use v dd in a continuous range of 3.0v to 5.5v without stopping the mcu, please contact your local toshiba office. (v ss = 0 v, topr = -10 to 40 c) parameter symbol pins ratings min max unit supply voltage v dd normal1, 2 modes 4.5 5.5 v input high level v ih1 except hysteresis input v dd 4.5 v v dd 0.70 v dd v ih2 hysteresis input v dd 0.75 input low level v il1 except hysteresis input v dd 4.5 v 0 v dd 0.30 v il2 except hysteresis input v dd 0.25 clock frequency fc xin, xout 1.0 16.0 mhz (v ss = 0 v, topr = -40 to 85 c) parameter symbol pins ratings min max unit supply voltage (condition 1) v dd fc = 16 mhz normal1, 2 modes idle0, 1, 2 modes 4.5 5.5 v fs = 32.768 khz slow1, 2 modes sleep0, 1, 2 modes stop mode supply voltage (condition 2) fc = 8 mhz normal1, 2 modes idle0, 1, 2 modes 3.0 3.6 fs = 32.768 khz slow1, 2 modes sleep0, 1, 2 modes stop mode input high level v ih1 except hysteresis input v dd 4.5 v v dd 0.70 v dd v ih2 hysteresis input v dd 0.75 v ih3 v dd < 4.5 v v dd 0.90 input low level v il1 except hysteresis input v dd 4.5 v 0 v dd 0.30 v il2 hysteresis input v dd 0.25 v il3 v dd < 4.5 v v dd 0.10 clock frequency fc xin, xout v dd = 3.0 to 3.6 v, 4.5 to 5.5v 1.0 8.0 mhz fc xin, xout v dd = 4.5 to 5.5 v 1.0 16.0 fs xtin, xtout v dd = 3.0 to 3.6 v, 4.5 to 5.5v 30.0 34.0 khz tentative
page 257 TMP86FS49FG 22.2.3 serial prom mode (v ss = 0 v, topr = -10 to 40 c) parameter symbol pins condition min max unit supply voltage v dd normal1, 2 modes 4.5 5.5 v input high voltage v ih1 except hysteresis input v dd 4.5 v v dd 0.70 v dd v ih2 hysteresis input v dd 0.75 input low voltage v il1 except hysteresis input v dd 4.5 v 0 v dd 0.30 v il2 hysteresis input v dd 0.25 clock frequency fc xin, xout 2.0 16.0 mhz tentative
page 258 22. electrical characteristics 22.1 absolute maximum ratings TMP86FS49FG 22.3 dc characteristics note 1: typical values show those at topr = 25 c and v dd = 5 v. note 2: input current (i in1 , i in3 ): the current through pull-up or pull-down resistor is not included. note 3: i dd does not include i ref . note 4: the supply currents of slow2 and sleep2 modes are equivalent to those of idle1 and idle2 modes. (v ss = 0 v, topr = -40 to 85 c) parameter symbol pins condition min typ. max unit hysteresis voltage v hs hysteresis input v dd = 5.5 v, v in = 5.5 v/0 v ?0.9? v input current i in1 test ??2 a i in2 sink open drain, tri?state port i in3 reset , stop input resistance r in reset pull?up 100 220 450 k ? output leakage current i lo1 sink open drain port v dd = 5.5 v, v out = 5.5 v ??2 a i lo2 tri?state port v dd = 5.5 v, v out = 5.5 v/0 v ??2 output high voltage v oh tri?state port v dd = 4.5 v, i oh = -0.7 ma 4.1 ? ? v output low voltage v ol except xout, p3, p5 v dd = 4.5 v, i ol = 1.6 ma ??0.4 output low curren i ol high current port (p3, p5 port) v dd = 4.5 v, v ol = 1.0 v ?20? ma supply current in normal1, 2 modes i dd v dd = 5.5 v v in = 5.3 v/0.2 v fc = 16 mhz fs = 32.768 khz when a program operates on flash memory ?12.620 supply current in idle0 mode ?6.37.5 supply current in idle 1, 2 modes ?7.610 supply current in slow1 mode v dd = 3.0 v v in = 2.8 v/0.2 v fs = 32.768 khz when a program operates on flash memory ?0.93 when a program operates on ram ?1021 a supply current in sleep1 mode ?4.516 supply current in sleep0 mode ?3.512 supply current in stop mode v dd = 5.5 v v in = 5.3 v/0.2 v ?0.510 tentative
page 259 TMP86FS49FG 22.4 ad characteristics note 1: the total error includes all errors except a quanitization error, and is defined as a maximum deviation from the ideal c on- version line. note 2: conversion time is defferent in recommended value by power supply voltage. note 3: the voltage to be input on the ain input pin must not exceed the range between v aref and v ss . if a voltage outside this range is input, conversion values will become unstable and conversion values of other channels will also be affected. note 4: analog reference voltage range: ? v aref = v aref - v ss note 5: when ad converter is not us ed, fix the avdd and varef pin on the v dd level. (v ss = 0.0 v, 4.5 v v dd 5.5 v, topr = -40 to 85 c) paramete symbol condition min typ. max unit analog reference voltage v aref a vdd - 1.0 ? a vdd v power supply voltage of analog control circuit a vdd v dd analog reference voltage range (note 4) ? v aref 3.5 ? ? analog input voltage v ain v ss ? v aref power supply current of analog refer- ence voltage i ref v dd = a vdd = v aref = 5.5 v v ss = a vss = 0.0 v ?0.61.0ma non linearity error v dd = a vdd = 5.0 v, v ss = a vss = 0.0 v v aref = 5.0 v ??2 lsb zero point error ??2 full scale error ??2 total error ??2 (v ss = 0 v, 3.0 v v dd 3.6 v, topr = -40 to 85 c) parameter symbol condition min typ. max unit analog reference voltage v aref a vdd - 1.0 ? a vdd v power supply voltage of analog control circuit a vdd v dd analog reference voltage range (note 4) ? v aref 2.5 ? ? analog input voltage v ain v ss ? v aref power supply current of analog refer- ence voltage i ref v dd = a vdd = v aref =3.6 v v ss = a vss = 0.0 v ?0.50.8ma non linearity error v dd = a vdd = 3.0 v v ss = a vss = 0.0 v v aref = 3.0 v ??2 lsb zero point error ??2 full scale error ??2 total error ??2 tentative
page 260 22. electrical characteristics 22.6 flash characteristics TMP86FS49FG 22.5 ac characteristics 22.6 flash characteristics 22.6.1 write/retenti on characteristics (v ss = 0 v, v dd = 4.5 v to 5.5 v, topr = -40 to 85 c) parameter symbol condition min typ. max unit machine cycle time tcy normal1, 2 modes 0.25 ? 4 s idle0, 1, 2 modes slow1, 2 modes 117.6 ? 133.3 sleep0, 1, 2 modes high-level clock pulse width t wch for external clock operation (xin input) fc = 16 mhz ? 31.25 ? ns low-level clock pulse width t wcl high-level clock pulse width t wsh for external clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low-level clock pulse width t wsl (v ss = 0 v, v dd = 3.0 v to 3.6 v, topr = -40 to 85 c) paramete symbol condition min typ. max unit machine cycle time t cy normal1, 2 modes 0.5 ? 4 s idle0, 1, 2 modes slow1, 2 modes 117.6 ? 133.3 sleep0, 1, 2 modes high-level clock pulse width t wch for external clock operation (xin input) fc = 8 mhz ? 62.5 ? ns low-level clock pulse width t wcl high-level clock pulse width t wsh for external clock operation (xtin input) fs = 32.768 khz ? 15.26 ? s low-level clock pulse width t wsl (v ss = 0 v) paramete condition min typ. max. unit number of guaranteed writes to flash memory v ss = 0 v, topr = -10 to 40 c ? ? 100 times tentative
page 261 TMP86FS49FG 22.7 recommended osc illating conditions note 1: to ensure stable oscillation, the resonator position, load capacitance, etc. must be appropriate. because these factors are greatly affected by board patterns, please be sure to evaluate operation on the board on which the device will actually be mounted. note 2: the product numbers and specifications of the resonators by murata manufacturing co., ltd. are subject to change. for up-to-date information, please refer to the following url: http://www.murata.co.jp/search/index.html 22.8 handling precaution - the solderability test conditions for lead-free produc ts (indicated by the suffix g in product name) are shown below. 1. when using the sn-63pb solder bath solder bath temperature = 230 c dipping time = 5 seconds number of times = once r-type flux used 2. when using the sn-3.0ag-0.5cu solder bath solder bath temperature = 245 c dipping time = 5 seconds number of times = once r-type flux used note: the pass criteron of the above test is as follows: solderability rate until forming 95 % - when using the device (oscillator) in plac es exposed to high electric fields such as cathode-ray tubes, we recommend elec- trically shielding the package in order to maintain normal operating condition. xtin xtout (2) low-frequency oscillation xin xout c 1 c 2 (1) high-frequency oscillation c 1 c 2 tentative
page 262 22. electrical characteristics 22.8 handling precaution TMP86FS49FG tentative

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